About the position
As an Engineer on our Hardware Team, you will co-design future hardware from different vendors for programmability and performance. You will work with our kernel, compiler and machine learning engineers to understand their needs related to ML techniques, algorithms, numerical approximations, programming expressivity, and compiler optimizations. You will evangelize these constraints with various vendors to develop future hardware architectures amenable for efficient training and inference. If you are excited about maximizing HBM bandwidth, optimizing for low arithmetic intensity, expressive SIMD ISA, low-precision formats, optimizing for memory hierarchies, simulating workloads at various resolutions of the hardware and evangelizing these ideas with hardware engineers, this is the perfect opportunity! This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.
Responsibilities
- Co-design future hardware for programmability and performance with our hardware vendors.
- Assist hardware vendors in developing optimal kernels and add support for it in our compiler.
- Develop performance estimates for critical kernels for different hardware configurations.
- Work with machine learning engineers, kernel engineers and compiler developers to understand their vision and needs from high performance accelerators.
- Manage communication and coordination with internal and external partners.
- Influence the roadmap of hardware partners to optimize them for OpenAI's workloads.
- Evaluate potential partners' accelerators and platforms.
- Build simulations and performance models to progressively improve decision making fidelity.
- As the scope of the role and team grows, understand and influence roadmaps for hardware partners for our datacenter networks, racks, and buildings.
Requirements
- 4+ years of industry experience, including experience harnessing compute at scale or building semiconductors.
- Strong experience in software/hardware co-design.
- Deep understanding of GPU and/or other AI accelerators.
- Experience with CUDA or a related accelerator programming language.
- Experience driving Machine Learning accuracy with low precision formats.
- Experience aligning future hardware with a well established HPC infrastructure.
- Familiar with the fundamentals of deep learning computing and chip microarchitecture.
- Able to actively collaborate with ML engineers, kernel writers and compiler developers.
Nice-to-haves
- PhD in Computer Science and Engineering with a specialization in Computer Architecture, Parallel Computing, Compilers or other Systems.
- Strong coding skills in C/C++ and Python.
- Strong understanding of LLMs and challenges related to their training and inference.
Benefits
- Relocation assistance to new employees.
- Hybrid work model of 3 days in the office per week.
